Overview of EP112
Master Bond EP112 is an ultra-low-viscosity, electrically insulating, two-component epoxy system ideal for various applications. This two-part case study series presents two use cases for EP112 for microelectronics fabrication processes when used to bond a silicon wafer to a glass substrate. Because the fabrication processes involved high temperature etching in KOH, an adhesive with high chemical resistance was required so that the pair did not de-bond during the etching step. By keeping the substrate pair bonded, EP112 played a key role in the successful fabrication of microelectronic devices.
Application #1: Bonding Silicon Wafer to Glass during Thin-Film Transfer to a Liquid Crystal Display
The demand for portable electronics has led to the development of silicon-on-insulator (SOI) materials to produce low-power systems with reduced parasitic capacitance. Although advanced SOI technologies provide superior performance, they use starting substrates that are much more expensive than standard bulk silicon wafers. Furthermore, circuits must be redesigned to be compatible with SOI fabrication processes.
To solve this, researchers at Lawrence Livermore National Laboratory developed an SOI process called START (Silicon Transfer to Arbitrary Substrate), which is capable of converting standard bulk silicon wafers with completed circuits into SOI-like configurations without significantly increasing costs. To do this, they used standard bulk silicon wafers after circuits were fabricated using conventional techniques, thus combining the advantages of bulk silicon electronics with those of SOI without increasing the costs. In this process, EP112 was chosen to bond a silicon wafer to a glass support substrate, which was eventually used to create a prototype liquid crystal display.
To read about the key parameters, requirements, and results, please download the full case study.
Application #2: EP112 Used to Bond Silicon Wafer to Glass Support Substrate During Wafer Thinning
Components of semiconductor electronics are susceptible to radiation damage, and although shielding them can help prevent this, isolated incidents with a single ionizing particle can still occur in so-called single-event upsets (SEUs). The severity of these events becomes worse as the device sizes decrease following Moore’s Law but attempts to overcome this often degrade the performance of the final integrated circuit (IC).
In the second paper of this two-part case study, researchers at Lawrence Livermore National Laboratory (LLNL) thinned a CMOS wafer substrate of a fabricated IC to reduce its susceptibility to SEUs. This was accomplished by significantly reducing the charge collection volume via a novel wafer-thinning process. As part of this new thinning process, EP112 was used to bond two substrates together, ensuring they remained bonded throughout the processing steps, including a harsh alkaline etching step.
To read about the key parameters, requirements, and results, please download the full case study.
Download full case study
References
McCarthy, Anthony M. “Application of a novel silicon thin-film transfer technology to a liquid crystal display.” (1997). https://doi.org/10.2172/469634.
McCarthy, Aaron J, and Thomas W. Sigmon. “Radiation Hardening of CMOS Microelectronics.” (2000). https://doi.org/10.2172/792429.